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Energy-Efficient Low-Latency Signed Multiplier for FPGA-Based Hardware Accelerators.

Research output: Contribution to journal › Research article › Contributed › peer-review

Contributors

Salim Ullah - , Chair of Processor Design (cfaed), Chair of Processor Design (Faculty of Computer Science) (Author)
Tuan Duy Anh Nguyen - , Chair of Processor Design (Faculty of Computer Science), Chair of Processor Design (cfaed) (Author)
Akash Kumar - , Chair of Processor Design (Faculty of Computer Science), Chair of Processor Design (cfaed) (Author)

Details

Original language	English
Article number	2
Pages (from-to)	41-44
Number of pages	4
Journal	IEEE Embed. Syst. Lett.
Volume	13
Issue number	2
Publication status	Published - 2021
Peer-reviewed	Yes

External IDs

Scopus	85107056481

Keywords

Research priority areas of TU Dresden

Information Technology and Microelectronics