Machine learning and Artificial Intelligence (AI) tasks have stretched traditional hardware to its limits. In-hardware computation is a novel approach that aims to run complex operations, such as matrix–vector multiplication, directly at the device level for increased efficiency. This work shows that the current of a fully CMOS-compatible Schottky barrier transistor can respond linearly to changes in either the source–gate or the source–drain voltage. This bi-linearity allows analog vector multiplication directly at the device level. Alongside the access to independent biasing through the additional back-gate offered by the FDSOI technology, which can be used to implement addition directly at the device level, it has great potential for in-hardware computation. The performance and multilevel operation are demonstrated by the electrical characterization of a two-transistor system, showcasing how the technology could be implemented in larger crossbar arrays. The potential for in-hardware computation is evaluated against a full in-software solution by comparing the inference performance on the Iris dataset. The simulated in-hardware schemes utilizing the back-biased Schottky barrier transistors can achieve the same accuracy as the digital implementation but with an order of magnitude less power dissipation per operation when compared to CMOS-based digital hardware accelerators proposed in the literature.