Reconfigurable Field-Effect Transistor (RFET) is an emerging technology that offers runtime reconfigurability between n-type and p-type operation modes. Its unique features, including intrinsic polymorphism, symmetric I–V characteristics, multiple independent gate control, and low leakage current, unlock new possibilities for designing energy-efficient logic circuits, particularly polymorphic ones well-suited for hardware security techniques such as logic locking. Although various RFET device realizations with different materials and structures have been proposed, only a few studies have developed standard cell libraries that enable the evaluation of large-scale circuits implemented with these technologies. Moreover, the existing libraries are not designed according to the design rules of well-established industrial processes. This paper presents standard cell libraries comprising both static and reconfigurable logic cells, enabling a complete RTL-to-GDSII flow for Three-Independent-Gate RFETs (TIG-RFETs), compatible with an industrial 22 nm FDSOI technology. We implement the circuits from the ISCAS’85 and EPFL’15 benchmark suites using our libraries within a commercial EDA tool flow and compare the synthesis results with their CMOS counterparts in the same technology node in terms of Power, Performance, and Area (PPA). The results demonstrate that TIG-RFETs can significantly reduce power consumption, though with a performance trade-off that limits the achievable clock frequency to a few MHz. Furthermore, we analyze the results to highlight the advantages and limitations of this implementation of TIG-RFETs and discuss potential future improvements.