Data Stream Processing in Networks-on-Chip

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Contributors

Abstract

Nowadays, the growing complexity in a wide variety of applications has led to the use of Multiprocessor Systems-on-Chip (MPSoCs). Networks-on-Chip (NoCs) have emerged as a scalable intra-chip communication technology for a high number of processing elements. However, the evolution of MPSoCs shows increasing communication requirements due to the growing number of PEs. This paper presents a novel Network-on-Chip microarchitecture that combines data transfers with data stream processing to exploit efficiently the transmission time. Data stream processing is enabled by a lightweight processing unit that is located within the transmission channels of the NoC. Thus, data can be processed by operations either in a processing element such as a MicroBlaze processor or inside the NoC while it is transferred. Operations executed by the NoC reduce the workload of the processing elements. In addition, the transmission time will be efficiently used. The novel microarchitecture is evaluated and compared to a state-of-the-art router on a Xilinx Zynq FPGA.

Details

Original languageEnglish
Title of host publication2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
EditorsRicardo Reis, Mircea Stan, Michael Huebner, Nikolaos Voros
PublisherIEEE Computer Society
Pages633-638
Number of pages6
ISBN (electronic)9781509067626
Publication statusPublished - 20 Jul 2017
Peer-reviewedYes

Publication series

SeriesIEEE Computer Society Annual Symposium on VLSI
ISSN2159-3477

Conference

Title2017 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2017
Duration3 - 5 July 2017
CityBochum, North Rhine-Westfalia
CountryGermany

External IDs

ORCID /0000-0003-2571-8441/work/142240452
Scopus 85027284422

Keywords

Keywords

  • Data Stream Processing, FPGA, Many Core Systems, MPSoC, Network-on-Chip

Library keywords