CMOS inverter with 4.7 ps gate delay fabricated on 90 nm SOI technology
Research output: Contribution to journal › Research article › Contributed › peer-review
Contributors
Abstract
Very low gate delays of 7.7 ps at 1 V supply and 4.7 ps at 2 V supplyhave been achieved for CMOS inverters fabricated on a 90 nm siliconon insulator technology. The results are measured with an optimisedCMOS ring oscillator. These are believed to be the lowest gate delaysreported to date for CMOS inverters at room temperature.
Details
| Original language | English |
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| Pages (from-to) | 1251-1252 |
| Number of pages | 2 |
| Journal | Electronics letters : the latest research in electronic engineering and technology |
| Volume | 40 |
| Issue number | 20 |
| Publication status | Published - 1 Jun 2004 |
| Peer-reviewed | Yes |
External IDs
| Scopus | 6444236974 |
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Keywords
Keywords
- CMOS integrated circuits, delay circuits, elemental semiconductors, high-speed integrated circuits, integrated circuit layout, invertors, oscillators, silicon-on-insulator 1 V, 2 V, 293 to 298 K, 4.7 ps, 7.7 ps, 90 nm, SOI technology, Si, gate delay fabrication, optimisedCMOS ring oscillator, room temperature, silicon on insulator technology, ultrafast CMOS inverter