CMOS inverter with 4.7 ps gate delay fabricated on 90 nm SOI technology
Publikation: Beitrag in Fachzeitschrift › Forschungsartikel › Beigetragen › Begutachtung
Beitragende
Abstract
Very low gate delays of 7.7 ps at 1 V supply and 4.7 ps at 2 V supplyhave been achieved for CMOS inverters fabricated on a 90 nm siliconon insulator technology. The results are measured with an optimisedCMOS ring oscillator. These are believed to be the lowest gate delaysreported to date for CMOS inverters at room temperature.
Details
| Originalsprache | Englisch |
|---|---|
| Seiten (von - bis) | 1251-1252 |
| Seitenumfang | 2 |
| Fachzeitschrift | Electronics letters : the latest research in electronic engineering and technology |
| Jahrgang | 40 |
| Ausgabenummer | 20 |
| Publikationsstatus | Veröffentlicht - 1 Juni 2004 |
| Peer-Review-Status | Ja |
Externe IDs
| Scopus | 6444236974 |
|---|
Schlagworte
Schlagwörter
- CMOS integrated circuits, delay circuits, elemental semiconductors, high-speed integrated circuits, integrated circuit layout, invertors, oscillators, silicon-on-insulator 1 V, 2 V, 293 to 298 K, 4.7 ps, 7.7 ps, 90 nm, SOI technology, Si, gate delay fabrication, optimisedCMOS ring oscillator, room temperature, silicon on insulator technology, ultrafast CMOS inverter