Application-specific processing using high-level synthesis for networks-on-chip
Research output: Contribution to conferences › Paper › Contributed › peer-review
Contributors
Details
Original language | English |
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Pages | 1-7 |
Number of pages | 7 |
Publication status | Published - 2017 |
Peer-reviewed | Yes |
External IDs
ORCID | /0000-0003-2571-8441/work/142240429 |
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Scopus | 85046969469 |
Keywords
Keywords
- field programmable gate arrays, multiprocessing systems, network-on-chip, application task, performance bottleneck, networks-on-chip, intra-chip communication technology, high-level synthesized processing units, application-specific operations, high-level synthesis, heterogeneous MultiProcessor Systems-on-Chip, NoC architecture, Ports (Computers), Computer architecture, System-on-chip, Network interfaces, Network-on-Chip, Manycore Systems, Application-Specific Processing, High-Level Synthesis, heterogeneous MPSoCs, processing element, PEs, application-specific processing, Dennard scaling, communication costs, MicroBlaze processor, FPGA, data transfers, Field programmable gate arrays, Programming, Multiaccess communication, MPSoC