Analyzing Cache Bandwidth on the Intel Core 2 Architecture
Research output: Contribution to conferences › Paper › Contributed › peer-review
Contributors
Abstract
Intel Core 2 processors are used in servers, desktops, and notebooks. They combine the Intel64 Instruction Set Architecture with a new microarchitecture based on Intel Core and are proclaimed by their vendor as the “world’s best processors”. In this paper, measured bandwidths between the computing cores and the different caches are presented. The STREAM benchmark1 is one of the most used kernels by scientists to determine the memory bandwidth. For deeper insight the STREAM benchmark was redesigned to get exact values for small problem sizes as well. This analysis gives hints to faster data access and compares performance results for standard and tuned routines on the Intel Core 2 Architecture.
Details
Original language | English |
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Pages | 365-372 |
Number of pages | 8 |
Publication status | Published - 2007 |
Peer-reviewed | Yes |
Conference
Title | International Parallel Computing Conference 2007 |
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Abbreviated title | ParCo 2007 |
Duration | 4 - 7 September 2007 |
Website | |
Degree of recognition | International event |
City | Juelich |
Country | Germany |
External IDs
ORCID | /0009-0003-0666-4166/work/151475590 |
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