Analyzing ARM CoreSight ETMV4.X Data Trace Stream with a Real-Time Hardware Accelerator
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Debugging and verification of modern SoCs is a vital step in realizing complex systems consisting of various components. Monitoring memory operations such as data transfer address and value is an essential debugging and verification feature. ARM CoreSight technology generates a specific debug trace stream standard to monitor the memory without affecting the normal execution of the system. This paper proposes a hardware architecture to analyze the debug trace stream in realtime. It is implemented on the Xilinx Virtex xc6vcx75t-2ff784 FPGA device and can operate at 125 MHz and occupies less than 8 % of the FPGA resources.
Details
Original language | English |
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Title of host publication | Proceedings of the 2021 Design, Automation and Test in Europe, DATE 2021 |
Place of Publication | Grenoble |
Publisher | IEEE Xplore |
Pages | 1606-1609 |
Number of pages | 4 |
ISBN (electronic) | 978-3-9819263-5-4 |
ISBN (print) | 978-1-7281-6336-9 |
Publication status | Published - 1 Feb 2021 |
Peer-reviewed | Yes |
Publication series
Series | Design, Automation and Test in Europe Conference and Exhibition (DATE) |
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ISSN | 1530-1591 |
External IDs
Scopus | 85111030895 |
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ORCID | /0000-0002-6286-5064/work/142240676 |
Mendeley | 87d3330b-0299-3bf3-ab45-fdef407fb7ac |
Keywords
ASJC Scopus subject areas
Keywords
- Debugging, System analysis and design, System verification, System-on-chips