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An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS

Research output: Contribution to journal › Research article › Contributed › peer-review

Contributors

Sebastian Höppner - , Chair of Highly-Parallel VLSI Systems and Neuro-Microelectronics (Author)
Dennis Walter - , Chair of Highly-Parallel VLSI Systems and Neuro-Microelectronics (Author)
Thomas Hocker - , Chair of Highly-Parallel VLSI Systems and Neuro-Microelectronics (Author)
Stephan Henker - , Chair of Highly-Parallel VLSI Systems and Neuro-Microelectronics (Author)
Stefan Hänzsche - , Chair of Highly-Parallel VLSI Systems and Neuro-Microelectronics (Author)
Daniel Sausner - (Author)
Georg Ellguth - , Chair of Highly-Parallel VLSI Systems and Neuro-Microelectronics (Author)
Jens-Uwe Schlüßler - , Chair of Highly-Parallel VLSI Systems and Neuro-Microelectronics (Author)
Holger Eisenreich - , Chair of Highly-Parallel VLSI Systems and Neuro-Microelectronics (Author)
René Schüffny - , Chair of Highly-Parallel VLSI Systems and Neuro-Microelectronics (Author)

Details

Original language	English
Pages (from-to)	749-762
Number of pages	14
Journal	IEEE Journal of Solid State Circuits
Volume	50
Issue number	3
Publication status	Published - 1 Mar 2015
Peer-reviewed	Yes

External IDs

Scopus	85027928698