Accelerating non-volatile/hybrid processor cache design space exploration for application specific embedded systems
Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed › peer-review
Contributors
Abstract
In this article, we propose a technique to accelerate non-volatile/hybrid of volatile and non-volatile processor cache design space exploration for application specific embedded systems. Utilizing a novel cache behavior modeling equation and a new accurate cache miss prediction mechanism, our proposed technique can accelerate NVM/hybrid FIFO processor cache design space exploration for SPEC CPU 2000 applications up to 249 times compared to the conventional approach.
Details
| Original language | English |
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| Title of host publication | 20th Asia and South Pacific Design Automation Conference |
| Publisher | IEEE, New York [u. a.] |
| Pages | 435-440 |
| Number of pages | 6 |
| ISBN (electronic) | 978-1-4799-7792-5 |
| Publication status | Published - 11 Mar 2015 |
| Peer-reviewed | Yes |
| Externally published | Yes |
Publication series
| Series | Asia and South Pacific Design Automation Conference (ASP-DAC) |
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| ISSN | 2153-6961 |
Conference
| Title | 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015 |
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| Duration | 19 - 22 January 2015 |
| City | Chiba |
| Country | Japan |