A Variability-Aware Compact Memristor Model for HfO2-based 1T1R ReRAM Devices

Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review

Contributors

  • Khang Phuoc Nguyen - , TUD Dresden University of Technology (Author)
  • Richard Schroedter - , Chair of Fundamentals of Electronics (Author)
  • Vasileios Ntinas - , Aalborg University (Author)
  • Emilio Perez Bosch Quesada - , Leibniz Institute for High Performance Microelectronics (Author)
  • Eduardo Perez - , Leibniz Institute for High Performance Microelectronics, Brandenburg University of Technology Cottbus-Senftenberg (Author)
  • Christian Wenger - , Leibniz Institute for High Performance Microelectronics, Brandenburg University of Technology Cottbus-Senftenberg (Author)
  • Ronald Tetzlaff - , Professor (rtd.) of Fundamentals of Electrical Engineering (Author)

Abstract

Memristive in-memory computing offers a promising pathway to overcome the von Neumann bottleneck, yet the lack of computationally efficient compact memristor models that simultaneously capture dynamic accuracy and inherent variability remains often a barrier to large-scale circuit design. This work presents a variability-aware physics-based compact model for HfO2 ReRAM devices fabricated in 130 nm 1T1R CMOS technology. The conduction term combines two transport mechanisms to achieve high accuracy in the low-voltage range, which is essential for inference operations in AI. The state dynamic mobility ranges over thirty orders of magnitude simulating the filament formation. To address cycle-to-cycle variability, the model is described by a stochastic differential equation formulation introducing Gaussian fluctuations to the activation energy barrier which reproduces the variability characteristics observed in potentiation and depression measurements. Validated against experimental quasi-static and pulse data, this model addresses the challenge of balancing between high-fidelity physical simulations and efficient EDA-compatible circuit-level design, enabling robust verification of neuromorphic architectures within standard CAD workflows.

Details

Original languageEnglish
Title of host publication2026 22nd International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design, SMACD 2026
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Number of pages4
ISBN (electronic)979-8-3195-0619-1
ISBN (print)979-8-3195-0620-7
Publication statusPublished - Aug 2026
Peer-reviewedYes

Publication series

SeriesInternational Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
ISSN2575-4874

Conference

Title22nd International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design
Abbreviated titleSMACD 2026
Conference number22
Duration29 June - 2 July 2026
Website
LocationHilton Dresden
CityDresden
CountryGermany

External IDs

ORCID /0000-0001-7436-0103/work/228956468
ORCID /0000-0003-3259-4571/work/228959797
ORCID /0000-0002-2367-5567/work/228960363

Keywords

Keywords

  • Compact memristor model, Emerging device simulation, Variability-aware neuromorphic computing