A Variability-Aware Compact Memristor Model for HfO2-based 1T1R ReRAM Devices

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung

Beitragende

  • Khang Phuoc Nguyen - , Technische Universität Dresden (Autor:in)
  • Richard Schroedter - , Professur für Grundlagen der Elektronik (Autor:in)
  • Vasileios Ntinas - , Aalborg University (Autor:in)
  • Emilio Perez Bosch Quesada - , Leibniz-Institut für innovative Mikroelektronik (Autor:in)
  • Eduardo Perez - , Leibniz-Institut für innovative Mikroelektronik, Brandenburgische Technische Universität Cottbus-Senftenberg (Autor:in)
  • Christian Wenger - , Leibniz-Institut für innovative Mikroelektronik, Brandenburgische Technische Universität Cottbus-Senftenberg (Autor:in)
  • Ronald Tetzlaff - , Seniorprofessor für Grundlagen der Elektrotechnik (Autor:in)

Abstract

Memristive in-memory computing offers a promising pathway to overcome the von Neumann bottleneck, yet the lack of computationally efficient compact memristor models that simultaneously capture dynamic accuracy and inherent variability remains often a barrier to large-scale circuit design. This work presents a variability-aware physics-based compact model for HfO2 ReRAM devices fabricated in 130 nm 1T1R CMOS technology. The conduction term combines two transport mechanisms to achieve high accuracy in the low-voltage range, which is essential for inference operations in AI. The state dynamic mobility ranges over thirty orders of magnitude simulating the filament formation. To address cycle-to-cycle variability, the model is described by a stochastic differential equation formulation introducing Gaussian fluctuations to the activation energy barrier which reproduces the variability characteristics observed in potentiation and depression measurements. Validated against experimental quasi-static and pulse data, this model addresses the challenge of balancing between high-fidelity physical simulations and efficient EDA-compatible circuit-level design, enabling robust verification of neuromorphic architectures within standard CAD workflows.

Details

OriginalspracheEnglisch
Titel2026 22nd International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design, SMACD 2026
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers (IEEE)
Seitenumfang4
ISBN (elektronisch)979-8-3195-0619-1
ISBN (Print)979-8-3195-0620-7
PublikationsstatusVeröffentlicht - Aug. 2026
Peer-Review-StatusJa

Publikationsreihe

ReiheInternational Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)
ISSN2575-4874

Konferenz

Titel22nd International Conference on Synthesis, Modeling, Analysis and Simulation Methods, and Applications to Circuits Design
KurztitelSMACD 2026
Veranstaltungsnummer22
Dauer29 Juni - 2 Juli 2026
Webseite
OrtHilton Dresden
StadtDresden
LandDeutschland

Externe IDs

ORCID /0000-0001-7436-0103/work/228956468
ORCID /0000-0003-3259-4571/work/228959797
ORCID /0000-0002-2367-5567/work/228960363

Schlagworte

ASJC Scopus Sachgebiete

Schlagwörter

  • Compact memristor model, Emerging device simulation, Variability-aware neuromorphic computing