A study for replacing CMOS gates by equivalent inverters

Research output: Contribution to book/conference proceedings/anthology/reportConference contributionContributedpeer-review

Contributors

  • Ch. Galani - , Aristotle University of Thessaloniki (Author)
  • A. Tsormpatzoglou - , Aristotle University of Thessaloniki (Author)
  • P. Chaourani - , Aristotle University of Thessaloniki (Author)
  • I. Messaris - , Department of Medical Physics and Biomedical Engineering, Aristotle University of Thessaloniki (Author)
  • S. Nikolaidis - , Aristotle University of Thessaloniki (Author)

Abstract

Analysis of the operation of CMOS gates is a complicated procedure. These gates can be replaced by equivalent inverters and therefore the expressions for the inverters are used to determine the electrical characteristics of the gates. In this paper, the equivalent inverter approach for replacing CMOS gates is evaluated. The NAND gate is used for this evaluation. Parametric expressions are created to determine the transistors widths of the equivalent inverter. A systematic method is used for incorporating the parameter dependencies in the expressions. Results verify the accuracy of this approach.

Details

Original languageEnglish
Title of host publication2015 IEEE International Symposium on Circuits and Systems (ISCAS)
PublisherIEEE Xplore
Pages1838-1841
Number of pages4
ISBN (electronic)978-1-4799-8391-9
Publication statusPublished - 27 May 2015
Peer-reviewedYes

Publication series

SeriesIEEE International Symposium on Circuits and Systems (ISCAS)
ISSN0271-4302

Conference

TitleIEEE International Symposium on Circuits and Systems 2015
Abbreviated titleISCAS 2015
Duration24 - 27 May 2015
CityLisbon
CountryPortugal

External IDs

Scopus 84946197392

Keywords

Keywords

  • Logic gates, Inverters, Delays, Integrated circuit modeling, Semiconductor device modeling, MOSFET