A study for replacing CMOS gates by equivalent inverters
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Analysis of the operation of CMOS gates is a complicated procedure. These gates can be replaced by equivalent inverters and therefore the expressions for the inverters are used to determine the electrical characteristics of the gates. In this paper, the equivalent inverter approach for replacing CMOS gates is evaluated. The NAND gate is used for this evaluation. Parametric expressions are created to determine the transistors widths of the equivalent inverter. A systematic method is used for incorporating the parameter dependencies in the expressions. Results verify the accuracy of this approach.
Details
| Original language | English |
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| Title of host publication | 2015 IEEE International Symposium on Circuits and Systems (ISCAS) |
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Pages | 1838-1841 |
| Number of pages | 4 |
| ISBN (electronic) | 978-1-4799-8391-9 |
| Publication status | Published - 27 May 2015 |
| Peer-reviewed | Yes |
Publication series
| Series | IEEE International Symposium on Circuits and Systems (ISCAS) |
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| ISSN | 0271-4302 |
Conference
| Title | IEEE International Symposium on Circuits and Systems 2015 |
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| Abbreviated title | ISCAS 2015 |
| Duration | 24 - 27 May 2015 |
| City | Lisbon |
| Country | Portugal |
External IDs
| Scopus | 84946197392 |
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Keywords
Keywords
- Logic gates, Inverters, Delays, Integrated circuit modeling, Semiconductor device modeling, MOSFET