A robustness study on self-alignment of thin-si dies using surface tension

Research output: Contribution to journalResearch articleContributedpeer-review

Contributors

  • Mitsuru Hiroshima - , Panasonic Factory Solutions Co., Ltd. (Author)
  • Kiyoshi Arita - , Panasonic Factory Solutions Co., Ltd. (Author)
  • Hiroshi Haji - , Panasonic Factory Solutions Co., Ltd. (Author)
  • Christof Landesberger - , Fraunhofer Research Institution for Microsystems and Solid State Technologies (EMFT) (Author)
  • Karlheinz Bock - , Fraunhofer Research Institution for Microsystems and Solid State Technologies (EMFT) (Author)

Abstract

We found that self-alignment accuracy was better than ±2 μm in the case with an initial offset of up to 1 mm. This method, driven by the surface tension force of the liquid, offers new technical solutions for both high accuracy chip bonding and low cost placement manner. Some important points, such as wetting behaviour, die release offset, and the influence of defects on a die, were studied in order to suggest approaches to robustness in this new technique.

Details

Original languageEnglish
Pages (from-to)227-230
Number of pages4
JournalJournal of Japan Institute of Electronics Packaging
Volume16
Issue number3
Publication statusPublished - Sept 2013
Peer-reviewedYes
Externally publishedYes

External IDs

ORCID /0000-0002-0757-3325/work/139064942

Keywords

ASJC Scopus subject areas

Keywords

  • Chip on Wafer, Self-Alignment, Surface Tension, Thin-Si Die