A robustness study on self-alignment of thin-si dies using surface tension
Research output: Contribution to journal › Research article › Contributed › peer-review
Contributors
Abstract
We found that self-alignment accuracy was better than ±2 μm in the case with an initial offset of up to 1 mm. This method, driven by the surface tension force of the liquid, offers new technical solutions for both high accuracy chip bonding and low cost placement manner. Some important points, such as wetting behaviour, die release offset, and the influence of defects on a die, were studied in order to suggest approaches to robustness in this new technique.
Details
Original language | English |
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Pages (from-to) | 227-230 |
Number of pages | 4 |
Journal | Journal of Japan Institute of Electronics Packaging |
Volume | 16 |
Issue number | 3 |
Publication status | Published - Sept 2013 |
Peer-reviewed | Yes |
Externally published | Yes |
External IDs
ORCID | /0000-0002-0757-3325/work/139064942 |
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Keywords
ASJC Scopus subject areas
Keywords
- Chip on Wafer, Self-Alignment, Surface Tension, Thin-Si Die