A robustness study on self-alignment of thin-si dies using surface tension

Publikation: Beitrag in FachzeitschriftForschungsartikelBeigetragenBegutachtung

Beitragende

  • Mitsuru Hiroshima - , Panasonic Factory Solutions Co., Ltd. (Autor:in)
  • Kiyoshi Arita - , Panasonic Factory Solutions Co., Ltd. (Autor:in)
  • Hiroshi Haji - , Panasonic Factory Solutions Co., Ltd. (Autor:in)
  • Christof Landesberger - , Fraunhofer Research Institution for Microsystems and Solid State Technologies (EMFT) (Autor:in)
  • Karlheinz Bock - , Fraunhofer Research Institution for Microsystems and Solid State Technologies (EMFT) (Autor:in)

Abstract

We found that self-alignment accuracy was better than ±2 μm in the case with an initial offset of up to 1 mm. This method, driven by the surface tension force of the liquid, offers new technical solutions for both high accuracy chip bonding and low cost placement manner. Some important points, such as wetting behaviour, die release offset, and the influence of defects on a die, were studied in order to suggest approaches to robustness in this new technique.

Details

OriginalspracheEnglisch
Seiten (von - bis)227-230
Seitenumfang4
FachzeitschriftJournal of Japan Institute of Electronics Packaging
Jahrgang16
Ausgabenummer3
PublikationsstatusVeröffentlicht - Sept. 2013
Peer-Review-StatusJa
Extern publiziertJa

Externe IDs

ORCID /0000-0002-0757-3325/work/139064942

Schlagworte

ASJC Scopus Sachgebiete

Schlagwörter

  • Chip on Wafer, Self-Alignment, Surface Tension, Thin-Si Die