A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
We present a low-power, energy efficient 32-bit RISCV microprocessor unit (MCU) in 22 nm FD-SOI. It achieves ultra-low leakage, even at high temperatures, by using an adaptive reverse body biasing (ABB) aware sign-off approach, a low-power optimized physical implementation, and custom SRAM macros with retention mode. We demonstrate the robustness of the chip with measurements over the full industrial temperature range, from - 40°C to 125°C. Our results match the state of the art (SOTA) with 4.8 uW / MHz at 50 MHz in active mode and surpass the SOTA in ultra-low-power retention mode.
Details
Original language | English |
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Title of host publication | 2023 20th International SoC Design Conference (ISOCC) |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 67-68 |
Number of pages | 2 |
ISBN (electronic) | 979-8-3503-2703-8 |
ISBN (print) | 979-8-3503-2704-5 |
Publication status | Published - 2023 |
Peer-reviewed | Yes |
Publication series
Series | International SoC Design Conference, ISOCC |
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Conference
Title | 20th International SoC Design Conference |
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Subtitle | Innovating the Future: Advancements in SoC and Emerging Technologies |
Abbreviated title | ISOCC 2023 |
Conference number | 20 |
Duration | 25 - 28 October 2023 |
Location | Ramada Plaza Jeju Hotel |
City | Jeju |
Country | Korea, Republic of |
Keywords
ASJC Scopus subject areas
Keywords
- adaptive body bias, IoT, retention SRAM, RISC-V