A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI

Research output: Contribution to book/conference proceedings/anthology/reportConference contributionContributedpeer-review

Contributors

Abstract

We present a low-power, energy efficient 32-bit RISCV microprocessor unit (MCU) in 22 nm FD-SOI. It achieves ultra-low leakage, even at high temperatures, by using an adaptive reverse body biasing (ABB) aware sign-off approach, a low-power optimized physical implementation, and custom SRAM macros with retention mode. We demonstrate the robustness of the chip with measurements over the full industrial temperature range, from - 40°C to 125°C. Our results match the state of the art (SOTA) with 4.8 uW / MHz at 50 MHz in active mode and surpass the SOTA in ultra-low-power retention mode.

Details

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference 2023, ISOCC 2023
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages67-68
Number of pages2
ISBN (electronic)979-8-3503-2703-8
Publication statusPublished - 2023
Peer-reviewedYes

Publication series

SeriesProceedings - International SoC Design Conference 2023, ISOCC 2023

Conference

Title20th International SoC Design Conference, ISOCC 2023
Duration25 - 28 October 2023
CityJeju
CountryKorea, Republic of

Keywords

Keywords

  • adaptive body bias, IoT, retention SRAM, RISC-V