A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
We present a low-power, energy efficient 32-bit RISCV microprocessor unit (MCU) in 22 nm FD-SOI. It achieves ultra-low leakage, even at high temperatures, by using an adaptive reverse body biasing (ABB) aware sign-off approach, a low-power optimized physical implementation, and custom SRAM macros with retention mode. We demonstrate the robustness of the chip with measurements over the full industrial temperature range, from - 40°C to 125°C. Our results match the state of the art (SOTA) with 4.8 uW / MHz at 50 MHz in active mode and surpass the SOTA in ultra-low-power retention mode.
Details
Originalsprache | Englisch |
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Titel | 2023 20th International SoC Design Conference (ISOCC) |
Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
Seiten | 67-68 |
Seitenumfang | 2 |
ISBN (elektronisch) | 979-8-3503-2703-8 |
ISBN (Print) | 979-8-3503-2704-5 |
Publikationsstatus | Veröffentlicht - 2023 |
Peer-Review-Status | Ja |
Publikationsreihe
Reihe | International SoC Design Conference, ISOCC |
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Konferenz
Titel | 20th International SoC Design Conference |
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Untertitel | Innovating the Future: Advancements in SoC and Emerging Technologies |
Kurztitel | ISOCC 2023 |
Veranstaltungsnummer | 20 |
Dauer | 25 - 28 Oktober 2023 |
Ort | Ramada Plaza Jeju Hotel |
Stadt | Jeju |
Land | Südkorea |
Schlagworte
ASJC Scopus Sachgebiete
Schlagwörter
- adaptive body bias, IoT, retention SRAM, RISC-V