A RISC-V MCU with adaptive reverse body bias and ultra-low-power retention mode in 22 nm FD-SOI

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

Abstract

We present a low-power, energy efficient 32-bit RISCV microprocessor unit (MCU) in 22 nm FD-SOI. It achieves ultra-low leakage, even at high temperatures, by using an adaptive reverse body biasing (ABB) aware sign-off approach, a low-power optimized physical implementation, and custom SRAM macros with retention mode. We demonstrate the robustness of the chip with measurements over the full industrial temperature range, from - 40°C to 125°C. Our results match the state of the art (SOTA) with 4.8 uW / MHz at 50 MHz in active mode and surpass the SOTA in ultra-low-power retention mode.

Details

OriginalspracheEnglisch
TitelProceedings - International SoC Design Conference 2023, ISOCC 2023
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers Inc.
Seiten67-68
Seitenumfang2
ISBN (elektronisch)979-8-3503-2703-8
PublikationsstatusVeröffentlicht - 2023
Peer-Review-StatusJa

Publikationsreihe

ReiheProceedings - International SoC Design Conference 2023, ISOCC 2023

Konferenz

Titel20th International SoC Design Conference, ISOCC 2023
Dauer25 - 28 Oktober 2023
StadtJeju
LandSüdkorea

Schlagworte

Schlagwörter

  • adaptive body bias, IoT, retention SRAM, RISC-V