A Random Linear Network Coding Platform MPSoC Designed in 22nm FDSOI
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Random linear network coding (RLNC) has great potential to improve security, reliability, energy efficiency and throughput of many applications in networking and storage applications. The high computation costs and power consumption caused a reduction of interest in RLNC research more than ten years ago. We present a distributed parallel computation platform aiming at making RLNC affordable and scalable enough to be deployed in real-life-sized applications. As key component of this platform, an MPSoC was developed, produced and measured in our lab. The design aims at high energy efficiency and utilizes a hierarchical communication system for scalability to reach data rates needed by real-life applications with a reasonable power budget. For example, our platform would suffice to equip a 36 Gb/s backplane, 20 W Ethernet switch with an RLNC accelerator on a power budget of 2.4 W, showing an energy efficiency of 37 pJ/b.
Details
Original language | English |
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Title of host publication | 2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) |
Publisher | IEEE Computer Society |
Pages | 217-222 |
Number of pages | 6 |
ISBN (electronic) | 978-1-6654-6605-9 |
ISBN (print) | 978-1-6654-6606-6 |
Publication status | Published - 6 Jul 2022 |
Peer-reviewed | Yes |
Publication series
Series | IEEE Computer Society Annual Symposium on VLSI |
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ISSN | 2159-3477 |
Conference
Title | 20th IEEE Computer Society Annual Symposium on VLSI |
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Abbreviated title | ISVLSI 2022 |
Conference number | 20 |
Duration | 4 - 6 July 2022 |
Website | |
Location | Aliathon Resort |
City | Pafos |
Country | Cyprus |
External IDs
Ieee | 10.1109/ISVLSI54635.2022.00050 |
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Keywords
Sustainable Development Goals
ASJC Scopus subject areas
Keywords
- low power, memory management, MPSoC, network coding, NoC, RLNC