A Random Linear Network Coding Platform MPSoC Designed in 22nm FDSOI

Research output: Contribution to book/Conference proceedings/Anthology/ReportConference contributionContributedpeer-review

Contributors

Abstract

Random linear network coding (RLNC) has great potential to improve security, reliability, energy efficiency and throughput of many applications in networking and storage applications. The high computation costs and power consumption caused a reduction of interest in RLNC research more than ten years ago. We present a distributed parallel computation platform aiming at making RLNC affordable and scalable enough to be deployed in real-life-sized applications. As key component of this platform, an MPSoC was developed, produced and measured in our lab. The design aims at high energy efficiency and utilizes a hierarchical communication system for scalability to reach data rates needed by real-life applications with a reasonable power budget. For example, our platform would suffice to equip a 36 Gb/s backplane, 20 W Ethernet switch with an RLNC accelerator on a power budget of 2.4 W, showing an energy efficiency of 37 pJ/b.

Details

Original languageEnglish
Title of host publication2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
PublisherIEEE Computer Society
Pages217-222
Number of pages6
ISBN (electronic)978-1-6654-6605-9
ISBN (print)978-1-6654-6606-6
Publication statusPublished - 6 Jul 2022
Peer-reviewedYes

Publication series

SeriesIEEE Computer Society Annual Symposium on VLSI
ISSN2159-3477

Conference

Title20th IEEE Computer Society Annual Symposium on VLSI
Abbreviated titleISVLSI 2022
Conference number20
Duration4 - 6 July 2022
Website
LocationAliathon Resort
CityPafos
CountryCyprus

External IDs

Ieee 10.1109/ISVLSI54635.2022.00050

Keywords

Sustainable Development Goals

Keywords

  • low power, memory management, MPSoC, network coding, NoC, RLNC

Library keywords