A Random Linear Network Coding Platform MPSoC Designed in 22nm FDSOI

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

Abstract

Random linear network coding (RLNC) has great potential to improve security, reliability, energy efficiency and throughput of many applications in networking and storage applications. The high computation costs and power consumption caused a reduction of interest in RLNC research more than ten years ago. We present a distributed parallel computation platform aiming at making RLNC affordable and scalable enough to be deployed in real-life-sized applications. As key component of this platform, an MPSoC was developed, produced and measured in our lab. The design aims at high energy efficiency and utilizes a hierarchical communication system for scalability to reach data rates needed by real-life applications with a reasonable power budget. For example, our platform would suffice to equip a 36 Gb/s backplane, 20 W Ethernet switch with an RLNC accelerator on a power budget of 2.4 W, showing an energy efficiency of 37 pJ/b.

Details

OriginalspracheEnglisch
Titel2022 IEEE Computer Society Annual Symposium on VLSI (ISVLSI)
Herausgeber (Verlag)IEEE Computer Society
Seiten217-222
Seitenumfang6
ISBN (elektronisch)978-1-6654-6605-9
ISBN (Print)978-1-6654-6606-6
PublikationsstatusVeröffentlicht - 6 Juli 2022
Peer-Review-StatusJa

Publikationsreihe

ReiheIEEE Computer Society Annual Symposium on VLSI
ISSN2159-3477

Konferenz

Titel20th IEEE Computer Society Annual Symposium on VLSI
KurztitelISVLSI 2022
Veranstaltungsnummer20
Dauer4 - 6 Juli 2022
Webseite
OrtAliathon Resort
StadtPafos
LandZypern

Externe IDs

Ieee 10.1109/ISVLSI54635.2022.00050

Schlagworte

Ziele für nachhaltige Entwicklung

Schlagwörter

  • low power, memory management, MPSoC, network coding, NoC, RLNC

Bibliotheksschlagworte