A Parametrizable High-Level Synthesis Library for Accelerating Neural Networks on FPGAs
Research output: Contribution to journal › Research article › Contributed › peer-review
Contributors
Details
| Original language | English |
|---|---|
| Pages (from-to) | 513-529 |
| Number of pages | 27 |
| Journal | Journal of Signal Processing Systems |
| Volume | 93 |
| Issue number | 5 |
| Publication status | Published - 2021 |
| Peer-reviewed | Yes |
External IDs
| Scopus | 85102810198 |
|---|---|
| ORCID | /0000-0003-2571-8441/work/142240528 |
Keywords
Keywords
- High-level synthesis, Hardware acceleration, Neural networks, FPGA, Library