A new twin flash™ Cell for 2 and 4 bit operation at 63nm feature size
Research output: Contribution to book/conference proceedings/anthology/report › Conference contribution › Contributed › peer-review
Contributors
Abstract
A 63nm Twin Flash memory cell with a size of 0.0225μm2 / 2 (4) bits is presented. The cell is proposed for data Flash products with 4 to 16Gbit densities. To achieve small cell areas, a buried bit line and an aggressive gate length of ∼100nm are the key features of this 63nm Twin Flash cell. The cell is well capable of 2 and 4 bit operation.
Details
| Original language | English |
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| Title of host publication | 2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA - Proceedings of Technical Papers |
| Publication status | Published - 2007 |
| Peer-reviewed | Yes |
| Externally published | Yes |
Publication series
| Series | International Symposium on VLSI Technology, Systems, and Applications |
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| ISSN | 1524-766X |
Conference
| Title | 2007 International Symposium on VLSI Technology, Systems and Applications, VLSI-TSA |
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| Duration | 23 - 25 April 2007 |
| City | Hsinchu |
| Country | Taiwan, Province of China |
External IDs
| ORCID | /0000-0003-3814-0378/work/156338391 |
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