In this work we present a new technique for designing high fan-in OR/NOR gates, suitable for static full swing logic styles like SCMOS. This circuit consumes a little static power but its dynamic power consumption is very small. In 500 MHZ its total power consumption is 2.7 times smaller than the power consumption of SCMOS in equal delay condition. The area needed by this method is below half the area needed by DCVSL or SCMOS. This circuit can work in low voltage as low as 1 V without significant performance degradation and is robust to process variations like threshold voltage variations. We present simulation results in 0.18 μm technology and compare performance of our method with other static logic styles.