A new static high fan-in OR-NOR gate structure suitable for low power CMOS VLSI
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
In this work we present a new technique for designing high fan-in OR/NOR gates, suitable for static full swing logic styles like SCMOS. This circuit consumes a little static power but its dynamic power consumption is very small. In 500 MHZ its total power consumption is 2.7 times smaller than the power consumption of SCMOS in equal delay condition. The area needed by this method is below half the area needed by DCVSL or SCMOS. This circuit can work in low voltage as low as 1 V without significant performance degradation and is robust to process variations like threshold voltage variations. We present simulation results in 0.18 μm technology and compare performance of our method with other static logic styles.
Details
Originalsprache | Englisch |
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Titel | International Conference on Microelectronics (ICM) 2005 |
Seiten | 102-105 |
Seitenumfang | 4 |
Publikationsstatus | Veröffentlicht - Dez. 2005 |
Peer-Review-Status | Ja |
Extern publiziert | Ja |
Konferenz
Titel | International Conference on Microelectronics 2005 |
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Kurztitel | ICM 2005 |
Veranstaltungsnummer | 17 |
Dauer | 13 - 15 Dezember 2005 |
Stadt | Islamabad |
Land | Pakistan |
Externe IDs
Scopus | 33847095940 |
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