This paper introduces a novel architecture for nearcache computation of posit dot products, aiming to address the challenges of data movement and computational inefficiencies in modern memory-intensive applications such as deep learning and scientific computing by combining the memory-efficiency of posit-arithmetic with the increased bandwidth of near-cache compute units. Utilizing the tightly-coupled coprocessor interface without requiring adjustments to the coherency protocols, the architecture is implemented with minimal hardware overhead, achieving up to $5.3 \times$ more throughput compared to the baseline for dot-product operations, which form the backbone of many neural network and matrix computation tasks. The architecture is evaluated using an FPGA prototype on real-world use cases.