A Multi-Bit PFD Architecture for ADPLLs with Built-In Jitter Self-Calibration
Research output: Contribution to conferences › Paper › Contributed › peer-review
Contributors
Details
| Original language | English |
|---|---|
| Pages | 1-5 |
| Publication status | Published - 2019 |
| Peer-reviewed | Yes |
Conference
| Title | IEEE International Symposium on Circuits and Systems 2019 |
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| Abbreviated title | ISCAS 2019 |
| Duration | 26 - 29 May 2019 |
| City | Sapporo |
| Country | Japan |
External IDs
| Scopus | 85066809348 |
|---|
Keywords
Keywords
- Phase frequency detector, Jitter, Phase locked loops, Calibration, Oscillators, Delay lines, Delays, All-digital phase-locked loop (ADPLL), LC-PLL, multi-bit PFD, low power, built-in self-calibration (BISC)