A Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore Systems
Research output: Contribution to conferences › Paper › Contributed › peer-review
Contributors
Details
Original language | English |
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Pages | 300-306 |
Number of pages | 7 |
Publication status | Published - 2022 |
Peer-reviewed | Yes |
Conference
Title | 32nd International Conference on Field Programmable Logic and Applications (FPL) |
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Conference number | |
Duration | 29 August - 2 September 2022 |
Location | |
City |