A Hybrid Memory/Accelerator Tile Architecture for FPGA-based RISC-V Manycore Systems

Research output: Contribution to conferencesPaperContributedpeer-review

Contributors

Details

Original languageEnglish
Pages300-306
Number of pages7
Publication statusPublished - 2022
Peer-reviewedYes

Conference

Title32nd International Conference on Field Programmable Logic and Applications (FPL)
Conference number
Duration29 August - 2 September 2022
Location
City