Systems on Chip forthe Internet of Things require fast-locking and robust clock generators to maximize theef-fectiveness of power management techniques suchas Dynamic Voltage and Frequency Scaling and duty-cycling. We present an ADPLL clock generator based onafully digital DCO architecture withan inherently linear and offset-free tuning characteristic that allowsfast lock-in within three and frequency changes during operation within two reference cycles. Measurements from a testchip in 22nm FDSOI CMOS technology show operation from 0.4to0.8V and 20to790 MHz. At0.5V,only107 JIW are consumed to generate a100 MHz clockwith59psRMS period jitter. Adaptive Body Biasing improves the jitter performance by upto40 % through compensation ofPVT variation.