A Class-J/F 60 GHz Power Amplifier with 42.3% Power Added Efficiency in FDSOI CMOS
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
A compact 60 GHz class-J/F amplifier in 22 nm FDSOI (fully depleted silicon on insulator) CMOS with high efficiencies at low supply voltages is analyzed and presented in this paper. It utilizes a pseudo-differential common source gain cell with a 0.8 dB insertion loss output transformer balun. At 1.1 V, 0.6 V, and 0.4 V supply, power added efficiencies of 42.3 %, 37.7% and 29.8%, and saturated output powers of 14.3 dBm, 9.5 dBm and 6.4 dBm, respectively, are measured. The active circuit area is only 0.0198 mm2.
Details
Original language | English |
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Title of host publication | 2024 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024 |
Publisher | Institute of Electrical and Electronics Engineers Inc. |
Pages | 123-126 |
Number of pages | 4 |
ISBN (electronic) | 9798350359473 |
Publication status | Published - 2024 |
Peer-reviewed | Yes |
Publication series
Series | Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium |
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ISSN | 1529-2517 |
Conference
Title | 2024 IEEE Radio Frequency Integrated Circuits Symposium |
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Abbreviated title | RFIC 2024 |
Duration | 16 - 18 June 2024 |
Website | |
Location | Walter E. Washington Convention Center |
City | Washington |
Country | United States of America |
External IDs
ORCID | /0000-0001-6778-7846/work/172083786 |
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Keywords
ASJC Scopus subject areas
Keywords
- 60 GHz, CMOS, millimetre wave circuits, nonlinear circuits, PAE, power amplifiers, silicon-on-insulator