A Class-J/F 60 GHz Power Amplifier with 42.3% Power Added Efficiency in FDSOI CMOS
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Beitragende
Abstract
A compact 60 GHz class-J/F amplifier in 22 nm FDSOI (fully depleted silicon on insulator) CMOS with high efficiencies at low supply voltages is analyzed and presented in this paper. It utilizes a pseudo-differential common source gain cell with a 0.8 dB insertion loss output transformer balun. At 1.1 V, 0.6 V, and 0.4 V supply, power added efficiencies of 42.3 %, 37.7% and 29.8%, and saturated output powers of 14.3 dBm, 9.5 dBm and 6.4 dBm, respectively, are measured. The active circuit area is only 0.0198 mm2.
Details
Originalsprache | Englisch |
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Titel | 2024 IEEE Radio Frequency Integrated Circuits Symposium, RFIC 2024 |
Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers Inc. |
Seiten | 123-126 |
Seitenumfang | 4 |
ISBN (elektronisch) | 9798350359473 |
Publikationsstatus | Veröffentlicht - 2024 |
Peer-Review-Status | Ja |
Publikationsreihe
Reihe | Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium |
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ISSN | 1529-2517 |
Konferenz
Titel | 2024 IEEE Radio Frequency Integrated Circuits Symposium |
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Kurztitel | RFIC 2024 |
Dauer | 16 - 18 Juni 2024 |
Webseite | |
Ort | Walter E. Washington Convention Center |
Stadt | Washington |
Land | USA/Vereinigte Staaten |
Externe IDs
ORCID | /0000-0001-6778-7846/work/172083786 |
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Schlagworte
ASJC Scopus Sachgebiete
Schlagwörter
- 60 GHz, CMOS, millimetre wave circuits, nonlinear circuits, PAE, power amplifiers, silicon-on-insulator