A 22 nm 10 TOPS Mixed-Precision Neural Network SoC for Image Processing with Energy-Efficient Dilated Convolution Support
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Abstract
Dilated convolutions have become popular in recent Deep Neural Networks (DNNs). However, they introduce additional zeros within the weights. To efficiently compute these layers within image processing DNNs, we implemented a 10 TOPS neural network SoC in 22 nm that supports dilated convolutions with reduced energy consumption. By exploiting this advantage, the energy can be reduced by a factor of 4.46 even for DNNs such as DeepLabV3+ with a majority of standard convolutional layers.
Details
| Original language | English |
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| Title of host publication | 2024 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS) |
| Publisher | Institute of Electrical and Electronics Engineers (IEEE) |
| Number of pages | 3 |
| ISBN (electronic) | 979-8-3503-8414-7 |
| ISBN (print) | 979-8-3503-8415-4 |
| Publication status | Published - 19 Apr 2024 |
| Peer-reviewed | Yes |
Conference
| Title | 27th IEEE Symposium in Low-Power and High-Speed Chips |
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| Abbreviated title | COOL CHIPS 27 |
| Conference number | 27 |
| Duration | 17 - 19 April 2024 |
| Website | |
| Location | The University of Tokyo |
| City | Tokyo |
| Country | Japan |
External IDs
| Scopus | 85194142861 |
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