A 7-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) with a sampling rate of 1.7 GS/s at a power consumption of 1.38 mW is presented. To prove the concept, the circuit was fabricated in a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology. It achieves an effective number of bits (ENOB) of 6.52 and a Walden figure-of-merit ( FoM_ W ) of 8.85 fJ/conv.-step. High sampling speed is achieved by introducing optimized logic, heavily employing dynamic logic for the critical building blocks as the memory cells and clock logic. Sharing of reset transistors between multiple memory cells further reduces the delay between comparator decision and switching of the capacitive digital-to-analog converter (CDAC) by 15%. For calibration of the comparator offset, tuning of the back-gate voltage available in the FD-SOI technology is investigated and employed. Compared with conventional approaches using a separate differential input pair, this reduces the comparator power dissipation by 5% and its noise by 10%. The ADC operates on a single 800-mV supply and uses an active area of 0.0022 mm 2. The ADC is the fastest > 6-bit ENOB single-channel SAR (or pipelined SAR) ADC, while at the same time achieving the best FoM_ W for any previously reported ADC above 1 GS/s.