A 1.38-mW 7-bit 1.7-GS/s Single-Channel Loop-Unrolled SAR ADC in 22-nm FD-SOI With 8.85 fJ/Conv.-Step for GHz Mobile Communication and Radar Systems

Publikation: Beitrag in FachzeitschriftForschungsartikelBeigetragenBegutachtung



A 7-bit single-channel loop-unrolled successive approximation register (SAR) analog-to-digital converter (ADC) with a sampling rate of 1.7 GS/s at a power consumption of 1.38 mW is presented. To prove the concept, the circuit was fabricated in a 22-nm fully depleted silicon-on-insulator (FD-SOI) technology. It achieves an effective number of bits (ENOB) of 6.52 and a Walden figure-of-merit () of 8.85 fJ/conv.-step. High sampling speed is achieved by introducing optimized logic, heavily employing dynamic logic for the critical building blocks as the memory cells and clock logic. Sharing of reset transistors between multiple memory cells further reduces the delay between comparator decision and switching of the capacitive digital-to-analog converter (CDAC) by 15%. For calibration of the comparator offset, tuning of the back-gate voltage available in the FD-SOI technology is investigated and employed. Compared with conventional approaches using a separate differential input pair, this reduces the comparator power dissipation by 5% and its noise by 10%. The ADC operates on a single 800-mV supply and uses an active area of 0.0022 mm2. The ADC is the fastest $>$ 6-bit ENOB single-channel SAR (or pipelined SAR) ADC, while at the same time achieving the best for any previously reported ADC above 1 GS/s.


Seiten (von - bis)3841-3851
FachzeitschriftIEEE transactions on microwave theory and techniques
PublikationsstatusVeröffentlicht - Sept. 2023

Externe IDs

Scopus 85149808239
WOS 000953743300001
Mendeley 01bf8bc6-4952-3ae6-a645-1106712fb21b


Forschungsprofillinien der TU Dresden


  • Registers, Clocks, Analog-digital conversion, Synthetic aperture radar, Power demand, Calibration, Voltage, Analog-digital conversion, Analog-to-digital converter (ADC), Asynchronous, Calibration, Clocks, Dynamic logic, Loop unrolled, Power demand, Registers, Single channel, Synthetic aperture radar, Voltage, successive approximation register (SAR), loop unrolled, single channel, asynchronous, dynamic logic