A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW

Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review

Contributors

  • Xin Zhang - , Chair of Physical Chemistry, Tokyo University of Agriculture (Author)
  • Po-Hung Chen - , Tokyo University of Agriculture (Author)
  • Yoshikatsu Ryu - , Semiconductor Technology Academic Research Center (STARC) (Author)
  • Koichi Ishida - , Chair of Circuit Design and Network Theory, Tokyo University of Agriculture (Author)
  • Yasuyuki Okuma - , Semiconductor Technology Academic Research Center (STARC) (Author)
  • Kazunori Watanabe - , Semiconductor Technology Academic Research Center (STARC) (Author)
  • Takayasu Sakurai - , Tokyo University of Agriculture (Author)
  • Makoto Takamiya - , Tokyo University of Agriculture (Author)

Abstract

A 0.45-V input, 0.4-V output on-chip gate boosted (OGB) buck converter with clock gated digital PWM controller in 40-nm CMOS achieved the highest efficiency to date with the output power less than 40μW. A linear delay trimming by a logarithmic stress voltage (LSV) scheme to compensate for the die-to-die delay variations of a delay line in the PWM controller with good controllability is also proposed.

Details

Original languageEnglish
Title of host publication2012 Symposium on VLSI Circuits (VLSIC)
PublisherInstitute of Electrical and Electronics Engineers (IEEE)
Pages194-195
Number of pages2
ISBN (print)978-1-4673-0845-8
Publication statusPublished - 15 Jun 2012
Peer-reviewedYes

Conference

Title2012 Symposium on VLSI Circuits (VLSIC)
Duration13 - 15 June 2012
LocationHonolulu, HI, USA

External IDs

Scopus 84866623183
ORCID /0000-0002-4152-1203/work/165453426

Keywords

Keywords

  • Delay, Stress, Clocks, Pulse width modulation, Logic gates, Delay lines, Voltage control