A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
A 0.45-V input, 0.4-V output on-chip gate boosted (OGB) buck converter with clock gated digital PWM controller in 40-nm CMOS achieved the highest efficiency to date with the output power less than 40μW. A linear delay trimming by a logarithmic stress voltage (LSV) scheme to compensate for the die-to-die delay variations of a delay line in the PWM controller with good controllability is also proposed.
Details
| Originalsprache | Englisch |
|---|---|
| Titel | 2012 Symposium on VLSI Circuits (VLSIC) |
| Herausgeber (Verlag) | Institute of Electrical and Electronics Engineers (IEEE) |
| Seiten | 194-195 |
| Seitenumfang | 2 |
| ISBN (Print) | 978-1-4673-0845-8 |
| Publikationsstatus | Veröffentlicht - 15 Juni 2012 |
| Peer-Review-Status | Ja |
Konferenz
| Titel | 2012 Symposium on VLSI Circuits (VLSIC) |
|---|---|
| Dauer | 13 - 15 Juni 2012 |
| Ort | Honolulu, HI, USA |
Externe IDs
| Scopus | 84866623183 |
|---|---|
| ORCID | /0000-0002-4152-1203/work/165453426 |
Schlagworte
Schlagwörter
- Delay, Stress, Clocks, Pulse width modulation, Logic gates, Delay lines, Voltage control