A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

  • Xin Zhang - , Professur für Physikalische Chemie, Tokyo University of Agriculture (Autor:in)
  • Po-Hung Chen - , Tokyo University of Agriculture (Autor:in)
  • Yoshikatsu Ryu - , Semiconductor Technology Academic Research Center (STARC) (Autor:in)
  • Koichi Ishida - , Professur für Schaltungstechnik und Netzwerktheorie, Tokyo University of Agriculture (Autor:in)
  • Yasuyuki Okuma - , Semiconductor Technology Academic Research Center (STARC) (Autor:in)
  • Kazunori Watanabe - , Semiconductor Technology Academic Research Center (STARC) (Autor:in)
  • Takayasu Sakurai - , Tokyo University of Agriculture (Autor:in)
  • Makoto Takamiya - , Tokyo University of Agriculture (Autor:in)

Abstract

A 0.45-V input, 0.4-V output on-chip gate boosted (OGB) buck converter with clock gated digital PWM controller in 40-nm CMOS achieved the highest efficiency to date with the output power less than 40μW. A linear delay trimming by a logarithmic stress voltage (LSV) scheme to compensate for the die-to-die delay variations of a delay line in the PWM controller with good controllability is also proposed.

Details

OriginalspracheEnglisch
Titel2012 Symposium on VLSI Circuits (VLSIC)
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers (IEEE)
Seiten194-195
Seitenumfang2
ISBN (Print)978-1-4673-0845-8
PublikationsstatusVeröffentlicht - 15 Juni 2012
Peer-Review-StatusJa

Konferenz

Titel2012 Symposium on VLSI Circuits (VLSIC)
Dauer13 - 15 Juni 2012
OrtHonolulu, HI, USA

Externe IDs

Scopus 84866623183
ORCID /0000-0002-4152-1203/work/165453426

Schlagworte

Schlagwörter

  • Delay, Stress, Clocks, Pulse width modulation, Logic gates, Delay lines, Voltage control