40 Gbit/s limiting output buffer in 80 nm CMOS
Research output: Contribution to journal › Research article › Contributed › peer-review
Contributors
Abstract
A 40 Gbit/s 1V limiting output buffer for an AC-coupled 50 /spl Omega/load with a differential output swing of 660 mV and a gain of 18dB is presented. A power consumption of only 24 mW and a simulatedrisetime of 11 ps are achieved by means of a systematic buffer optimisation.
Details
Original language | English |
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Pages (from-to) | 1051-1053 |
Number of pages | 3 |
Journal | Electronics letters : the latest research in electronic engineering and technology |
Volume | 41 |
Issue number | 19 |
Publication status | Published - 1 Mar 2005 |
Peer-reviewed | Yes |
External IDs
Scopus | 25444474207 |
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Keywords
Keywords
- CMOS digital integrated circuits, buffer circuits, driver circuits, limiters 1 V, 11 ps, 18 dB, 24 mW, 40 Gbit/s, 50 ohm, 660 mV, 80nm, AC coupling, CMOS, buffer optimisation, limiting output buffer, power consumption