A 1.8 GHz phase-locked loop (PLL) with a self-calibration circuit implemented in 0.35 μm CMOS process is presented. The calibration circuit continuously adjusts the delay mismatches among the delay cells in a ring-type voltage controlled oscillator (VCO) and automatically cancels the phase offsets in the multi-phase clock signals generated from the VCO. An edge-combining fractional-N frequency synthesizer with the self-calibrated PLL has been implemented and successfully eliminates -13 dBc fractional spur occurred by the delay mismatches in the VCO.