1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme

Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review

Contributors

  • K. Kanda - , Tokyo University of Agriculture (Author)
  • D.D. Antono - , Tokyo University of Agriculture (Author)
  • K. Ishida - , Chair of Circuit Design and Network Theory, The University of Tokyo, Tokyo University of Agriculture (Author)
  • H. Kawaguchi - , Tokyo University of Agriculture (Author)
  • T. Kuroda - , Keio University (Author)
  • T. Sakurai - , Tokyo University of Agriculture (Author)

Abstract

A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm/sup 2/. The interface utilizes capacitively coupled contactless minipads, return-to-half-V/sub 00/ signaling and sense amplifying F/F. The measured test chip fabricated in 0.35/spl mu/m CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.

Details

Original languageEnglish
Title of host publication2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.
PublisherIEEE
Pages186-487
Number of pages302
ISBN (print)0-7803-7707-9
Publication statusPublished - 13 Feb 2003
Peer-reviewedYes

Conference

Title2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.
Duration13 February 2003
LocationSan Francisco, CA, USA

External IDs

ORCID /0000-0002-4152-1203/work/165453380

Keywords

Keywords

  • Electrostatic discharge, Capacitors, Coupling circuits, Protection, Capacitance, Transmitters, Personal communication networks, Bandwidth, Very large scale integration, Driver circuits