1.27Gb/s/pin 3mW/pin wireless superconnect (WSC) interface scheme

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung

Beitragende

  • K. Kanda - , Tokyo University of Agriculture (Autor:in)
  • D.D. Antono - , Tokyo University of Agriculture (Autor:in)
  • K. Ishida - , Professur für Schaltungstechnik und Netzwerktheorie, The University of Tokyo, Tokyo University of Agriculture (Autor:in)
  • H. Kawaguchi - , Tokyo University of Agriculture (Autor:in)
  • T. Kuroda - , Keio University (Autor:in)
  • T. Sakurai - , Tokyo University of Agriculture (Autor:in)

Abstract

A low-power high-speed chip-to-chip interface scheme is described having a density of 625pins/mm/sup 2/. The interface utilizes capacitively coupled contactless minipads, return-to-half-V/sub 00/ signaling and sense amplifying F/F. The measured test chip fabricated in 0.35/spl mu/m CMOS delivers up to 1.27Gb/s/pin at 3mW/pin.

Details

OriginalspracheEnglisch
Titel2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers (IEEE)
Seiten186-487
Seitenumfang302
ISBN (Print)0-7803-7707-9
PublikationsstatusVeröffentlicht - 13 Feb. 2003
Peer-Review-StatusJa

Konferenz

Titel2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC.
Dauer13 Februar 2003
OrtSan Francisco, CA, USA

Externe IDs

ORCID /0000-0002-4152-1203/work/165453380

Schlagworte

Schlagwörter

  • Electrostatic discharge, Capacitors, Coupling circuits, Protection, Capacitance, Transmitters, Personal communication networks, Bandwidth, Very large scale integration, Driver circuits