10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS
Research output: Contribution to book/Conference proceedings/Anthology/Report › Conference contribution › Contributed › peer-review
Contributors
Details
Original language | English |
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Title of host publication | 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC) |
Publisher | IEEE Xplore |
Pages | 188-189 |
Number of pages | 2 |
ISBN (electronic) | 978-1-4799-0920-9 |
ISBN (print) | 978-1-4799-0918-6 |
Publication status | Published - 1 Feb 2014 |
Peer-reviewed | Yes |
Publication series
Series | IEEE International Conference on Solid-State Circuits (ISSCC) |
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External IDs
Scopus | 84898079313 |
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Keywords
Keywords
- 4G mobile communication, CMOS integrated circuits, iterative decoding, multiprocessing systems, processor scheduling, system-on-chip, ASIC, ASIP, CMOS, CoreManager, Tomahawk2 MPSoC, application specific hardware unit, design constraints, dynamic scheduler, energy-aware dynamic scheduling, general purpose processor, heterogeneous SDR MPSoC, hierarchical power management, iterative detection decoding, power efficiency, power gating, processing elements, processing performance, runtime scheduling, size 65 nm, Baseband, Computer architecture, Dynamic scheduling, Engines, Forward error correction, MIMO, Reduced instruction set computing