10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung

Beitragende

Details

OriginalspracheEnglisch
Titel2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC)
Herausgeber (Verlag)IEEE Xplore
Seiten188-189
Seitenumfang2
ISBN (elektronisch)978-1-4799-0920-9
ISBN (Print)978-1-4799-0918-6
PublikationsstatusVeröffentlicht - 1 Feb. 2014
Peer-Review-StatusJa

Publikationsreihe

ReiheIEEE International Conference on Solid-State Circuits (ISSCC)

Externe IDs

Scopus 84898079313

Schlagworte

Schlagwörter

  • 4G mobile communication, CMOS integrated circuits, iterative decoding, multiprocessing systems, processor scheduling, system-on-chip, ASIC, ASIP, CMOS, CoreManager, Tomahawk2 MPSoC, application specific hardware unit, design constraints, dynamic scheduler, energy-aware dynamic scheduling, general purpose processor, heterogeneous SDR MPSoC, hierarchical power management, iterative detection decoding, power efficiency, power gating, processing elements, processing performance, runtime scheduling, size 65 nm, Baseband, Computer architecture, Dynamic scheduling, Engines, Forward error correction, MIMO, Reduced instruction set computing

Bibliotheksschlagworte