PRFloor: An automatic floorplanner for partially reconfigurable FPGA systems

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

Abstract

Partial reconfiguration (PR) is gaining more attention from the research community because of its flexibility in dynamically changing some parts of the system at runtime. However, the current PR tools need the designer's involvement in manually specifying the shapes and locations for the PR regions (PRRs). It requires not only deep knowledge of the FPGA device, the system architecture, but also many trial-and-error attempts to find the best-possible floorplan. Therefore, many research works have been conducted to propose automatic floorplanners for PR systems. However, one of the most significant limitations of those works is that they only consider the PRRs and ignore all other static modules. In this paper, we propose a novel PR floorplanner called PRFloor. It takes into account all components in the system. The main ideas behind PRFloor are the unique recursive pseudo-bipartitioning heuristic using a new, simple, yet effective Nonlinear Integer Programming-based bipartitioner. The PRFloor performs very well in the experiments with various synthetic PR system setups with up to 130 modules, 24 PRRs and 85% of the FPGA resource. The average maximum clock frequency obtained for the actual PR systems implemented using PRFloor is even 3% higher than the similar systems without PR capability.

Details

OriginalspracheEnglisch
TitelFPGA 2016 - Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays
Herausgeber (Verlag)Association for Computing Machinery, Inc
Seiten149-158
Seitenumfang10
ISBN (elektronisch)9781450338561
PublikationsstatusVeröffentlicht - 21 Feb. 2016
Peer-Review-StatusJa

Konferenz

Titel2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA 2016
Dauer21 - 23 Februar 2016
StadtMonterey
LandUSA/Vereinigte Staaten

Schlagworte

Forschungsprofillinien der TU Dresden

Schlagwörter

  • Bipartition, FPGA floorplan, NLP, Partial reconfiguration