The impact of strain, induced by nanoindentation, on integrated circuit performance is measured. Localized strain caused by chip-package interaction alters the charge carrier mobility in the transistor channel due to the piezoresistive effect. Instrumented indentation enables to induce controlled localized loads with high lateral precision, and it is used to apply consecutive loading conditions to a single test device. Newly designed ring oscillator test structures manufactured in 22 nm FDSOI technology are used as a sensor to monitor the strain effect on transistor performance. Novel tip geometries provide insight into the direction dependent strain impact. Strain/stress fields at transistor level are determined by complementary FEM simulation. Board bending experiments with uniaxial stress/strain conditions are performed to verify the approach. The established correlation of mechanical load and device performance is used to provide an estimate for the effect of package related stress on transistor performance.