Isothermal Shock Testing on Flip-Chip Interconnects

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

Abstract

Environmental stress testing has always been an important topic for the electronics industry and several test methods were developed. Among those, mechanical tests like shock and vibration tests are of prior interest in the field of automotive, avionics and industrial electronics since this load type occurs in use conditions. As of today, both mechanical loads are tested separately not necessarily using identical specimens. For shock testing JEDEC B110 or B111 designs and several custom designs, mostly in a rectangular shape, are common. However, with most of these designs efficient failure generation with shaker usage is not possible. This includes the aims of failure mechanism analysis and time to failure data acquisition. This paper shows a newly developed test vehicle suitable for shock as well as other mechanical load conditions and capable of simultaneous testing of multiple components. In the current design version 9 flipchips with a size of 2.9×4.9 mm2 were mounted and tested till failure under shock loads with 130 g amplitude and 2 ms pulse width at room temperature. In addition to that, tests were repeated at temperatures of -40 °C and 125 °C. Lifetime data has been acquired through online monitoring of solder joint resistance. Stress levels were monitored through strain gauges at the backside of the test vehicles and allowed for stress monitoring during shock events, which showed a peak-to-peak strain of 820 μm/m at room temperature, 781 μm/m at -40 °C and 742 μm/m at 125 °C. Failure analysis data gathered by cross sectioning after the tests showed crack initiation, propagation and complete cracks near the IMC on both flip-chip side and board side of the solder joints.

Details

OriginalspracheEnglisch
TitelProceedings - IEEE 75th Electronic Components and Technology Conference, ECTC 2025
Herausgeber (Verlag)Institute of Electrical and Electronics Engineers (IEEE)
Seiten737-742
Seitenumfang6
ISBN (elektronisch)979-8-3315-3932-0
PublikationsstatusVeröffentlicht - 2025
Peer-Review-StatusJa

Publikationsreihe

ReiheProceedings - Electronic Components and Technology Conference
ISSN0569-5503

Konferenz

Titel75th IEEE Electronic Components and Technology Conference
KurztitelECTC 2025
Veranstaltungsnummer75
Dauer27 - 30 Mai 2025
Webseite
OrtGaylord Texan Resort & Convention Center
StadtDallas
LandUSA/Vereinigte Staaten

Externe IDs

ORCID /0000-0002-0757-3325/work/190133624
ORCID /0000-0001-9720-0727/work/192581612

Schlagworte

Schlagwörter

  • failure mode analysis, isothermal testing, reliability, shock testing