The ESD Association standards working group 5.3.2 is analyzing the procedure and stress that is applied to a device under test (DUT) using a socketed discharge model (SDM) test system, formerly referred to as socketed CDM. Our final goal is to define an SDM tester specification that will guarantee test result reproducibility across different test equipment. This paper investigates the effect of tester background parasitics on the discharge current waveforms of an SDM tester. Characteristic waveforms were studied and SDM testing was performed on actual devices. It is shown that SDM tester parasitics determine the stress applied to the DUT. This directly impacts the SDM failure threshold voltage levels and may lead to miscorrelation and non-reproducibility of test results across different SDM test systems. This paper empirically determines the relative contributions of the various tester parasitics to the total stress applied to the DUT. Our investigations indicate that the tester provides a 10-20 pF parasitic capacitance discharge into each pin of the device. Tester background parasitic elements play such an important role in the SDM discharge event that correlation between test systems built by different manufacturers is unlikely without completely duplicating a particular tester.