The electrostatic discharges (ESD) of grounded-gate nMOS structures was investigated for a standard 0.25 μm CMOS epitaxial layer based technology. Very high It2-values were obtained, in the range between 10 and 15 mA/μm, and HBM thresholds of 15-30 V/μm. Unexpectedly however, the shortest gate lengths showed lower thresholds that lead to an optimum performance for gate lengths of about 1 μm. Failure analysis and device simulations confirmed the gate length effect as a real device effect under the CMOS technology and the device design. Finally, the strong impact of the failure criterion on the second breakdown current was demonstrated, highlighting the need for a standardization of the TLP technology and the It2 measurement.