Electrical behaviour of Flip-Chip bonded thin silicon chip-on-foil assembly during bending

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung

Beitragende

  • Nagarajan Palavesam - , Professur für Aufbau- und Verbindungstechnik der Elektronik, Fraunhofer Research Institution for Microsystems and Solid State Technologies (EMFT), Technische Universität München (Autor:in)
  • Detlef Bonfert - , Fraunhofer Research Institution for Microsystems and Solid State Technologies (EMFT) (Autor:in)
  • Waltraud Hell - , Fraunhofer Research Institution for Microsystems and Solid State Technologies (EMFT) (Autor:in)
  • Christof Landesberger - , Fraunhofer Research Institution for Microsystems and Solid State Technologies (EMFT) (Autor:in)
  • Horst Gieser - , Fraunhofer Research Institution for Microsystems and Solid State Technologies (EMFT) (Autor:in)
  • Christoph Kutter - , Fraunhofer Research Institution for Microsystems and Solid State Technologies (EMFT) (Autor:in)
  • Karlheinz Bock - , Professur für Aufbau- und Verbindungstechnik der Elektronik, Technische Universität Dresden, Struktur- und Werkstoffmechanikforschung Dresden GmbH an der Technischen Universität Dresden (SWM) (Autor:in)

Abstract

We present our results on the analysis of electrical performance of Flip-Chip bonded thin Silicon chip-on-foil assemblies during bending. A custom made bending machine was utilized to bend the test samples and the electrical resistance of the Daisy Chain structures were measured during the tests. Resistance measurements confirmed the failure of the test samples after about 2000 bending cycles.

Details

OriginalspracheDeutsch
Titel2015 IEEE 21st International Symposium for Design and Technology in Electronic Packaging (SIITME)
Herausgeber (Verlag)IEEE
Seiten367-372
Seitenumfang6
ISBN (Print)978-1-5090-0331-0
PublikationsstatusVeröffentlicht - 25 Okt. 2015
Peer-Review-StatusJa

Konferenz

Titel2015 IEEE 21st International Symposium for Design and Technology in Electronic Packaging (SIITME)
Dauer22 - 25 Oktober 2015
OrtBrasov, Romania

Externe IDs

Scopus 84960385804
ORCID /0000-0002-0757-3325/work/139064860

Schlagworte

Schlagwörter

  • Electrical resistance measurement, Resistance, Stress, Performance evaluation, Assembly, Semiconductor device measurement, Aluminum