Capacitive coupled TLP (CC-TLP) and the correlation with the CDM

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

  • Heinrich Wolf - , Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration (Autor:in)
  • Horst Gieser - , Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration (Autor:in)
  • Karlheinz Bock - , Professur für Aufbau- und Verbindungstechnik der Elektronik, Fraunhofer-Institut für Zuverlässigkeit und Mikrointegration (Autor:in)
  • Agha Jahanzeb - , Texas Instruments (Autor:in)
  • Charvaka Duvvury - , Texas Instruments (Autor:in)
  • Yen-Yi Lin - , Texas Instruments (Autor:in)

Abstract

Capacitive Coupled Transmission Line Pulsing (CC-TLP) has successfully identified a known CDM weakness at the RF inputs of two different 90 nm CMOS RF products. The presented study compares electrical and physical failure signatures for packaged devices and even for devices stressed at wafer level. The peak stress currents resulting in a failure as well as the failure signatures correlate very well for CDM and CC-TLP. The results also support the application of a single stress per pin with the potential to save many hours of test time without loosing confidence.

Details

OriginalspracheDeutsch
Titel2009 31st EOS/ESD Symposium
Herausgeber (Verlag)IEEE
Seiten1-8
Seitenumfang8
ISBN (Print)978-1-58537-176-1
PublikationsstatusVeröffentlicht - 4 Sept. 2009
Peer-Review-StatusJa

Konferenz

Titel2009 31st EOS/ESD Symposium
Dauer30 August - 4 September 2009
OrtAnaheim, CA, USA

Externe IDs

ORCID /0000-0002-0757-3325/work/139064832

Schlagworte

Schlagwörter

  • Stress, Circuit testing, Packaging, Wafer scale integration, CMOS technology, Protection, Electrostatic discharge, Capacitance, Transmission lines, Radio frequency