Automated Hardening of Deep Neural Network Architectures
Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/Gutachten › Beitrag in Konferenzband › Beigetragen › Begutachtung
Beitragende
Abstract
Designing optimal neural network (NN) architectures is a difficult and time-consuming task, especially when error resiliency and hardware efficiency are considered simultaneously. In our paper, we extend neural architecture search (NAS) to also optimize a NN’s error resilience and hardware related metrics in addition to classification accuarcy. To this end, we consider the error sensitivity of a NN on the architecture-level during NAS and additionally incorporate checksums into the network as an external error detection mechanism. With an additional computational overhead as low as 17 % for the discovered architectures, checksums are an efficient method to effectively enhance the error resilience of NNs. Furthermore, the results show that cell-based NN architectures are able to maintain their error resilience characteristics when transferred to other tasks.
Details
| Originalsprache | Englisch |
|---|---|
| Titel | Safety Engineering, Risk, and Reliability Analysis; Research Posters |
| Herausgeber (Verlag) | The American Society of Mechanical Engineers(ASME) |
| Band | 13 |
| ISBN (elektronisch) | 978-0-7918-8569-7 |
| Publikationsstatus | Veröffentlicht - 2021 |
| Peer-Review-Status | Ja |
Publikationsreihe
| Reihe | ASME International Mechanical Engineering Congress and Exposition, Proceedings (IMECE) |
|---|
Konferenz
| Titel | ASME 2021 International Mechanical Engineering Congress and Exposition |
|---|---|
| Kurztitel | IMECE 2021 |
| Dauer | 1 - 5 November 2021 |
| Bekanntheitsgrad | Internationale Veranstaltung |
| Ort | Online |
| Land | USA/Vereinigte Staaten |
Schlagworte
ASJC Scopus Sachgebiete
Schlagwörter
- Error Resilience, Neural Architecture Search, Neural Network Hardware, Random Hardware Faults