Adaptive and transparent cache bypassing for GPUs

Publikation: Beitrag in Buch/Konferenzbericht/Sammelband/GutachtenBeitrag in KonferenzbandBeigetragenBegutachtung

Beitragende

  • Ang Li - , Eindhoven University of Technology, National University of Singapore (Autor:in)
  • Gert Jan Van Den Braak - , Eindhoven University of Technology (Autor:in)
  • Akash Kumar - , Professur für Prozessorentwurf (Prozessor Design) (cfaed) (Autor:in)
  • Henk Corporaal - , Eindhoven University of Technology (Autor:in)

Abstract

In the last decade, GPUs have emerged to be widely adopted for general-purpose applications. To capture on-chip locality for these applications, modern GPUs have integrated multilevel cache hierarchy, in an attempt to reduce the amount and latency of the massive and sometimes irregular memory accesses. However, inferior performance is frequently attained due to serious congestion in the caches results from the huge amount of concurrent threads. In this paper, we propose a novel compile-time framework for adaptive and transparent cache bypassing on GPUs. It uses a simple yet effective approach to control the bypass degree to match the size of applications' runtime footprints. We validate the design on seven GPU platforms that cover all existing GPU generations using 16 applications from widely used GPU benchmarks. Experiments show that our design can significantly mitigate the negative impact due to small cache sizes and improve the overall performance. We analyze the performance across different platforms and applications. We also propose some optimization guidelines on how to efficiently use the GPU caches.

Details

OriginalspracheEnglisch
TitelSC '15: Proceedings of the International Conference for High Performance Computing, Networking, Storage and Analysis
Herausgeber (Verlag)Association for Computing Machinery (ACM), New York
Seiten1-12
Seitenumfang12
ISBN (elektronisch)978-1-4503-3723-6
PublikationsstatusVeröffentlicht - 15 Nov. 2015
Peer-Review-StatusJa

Publikationsreihe

ReiheSC: The International Conference for High Performance Computing, Networking, Storage, and Analysis
Band15-20-November-2015
ISSN2167-4329

Konferenz

TitelInternational Conference for High Performance Computing, Networking, Storage and Analysis, SC 2015
Dauer15 - 20 November 2015
StadtAustin
LandUSA/Vereinigte Staaten

Schlagworte

Forschungsprofillinien der TU Dresden

Schlagwörter

  • cache bypassing, GPUs, thread throttling